The present invention is directed to a capacitive structure formed on a semiconductor substrate. In particular, the present invention is directed to a vertical capacitor structure applied to a semiconductor substrate having a large surface area to establish large capacitance, and a method for forming such a structure.
As DRAM (Dynamic Random Access Memory) devices are increased in memory capacity to 64 Megabytes of memory capacity and beyond, vertical, stacked capacitor structures are increasingly employed to continue to meet the charge storage requirements for such devices while continuing to reduce the area occupied by the device in keeping with the continuing trend toward smaller devices.
Two basic capacitor structures have been employed to date in memory devices, such as DRAM's: trench capacitors and stacked capacitors. Trench capacitors provide a capacitive structure within a trench "dug" into a semiconductor substrate which carries gating transistors and capacitive structures. Stacked capacitors are formed upon the surface of a semiconductor substrate above the substrate surface and may be "stacked" higher as greater capacitance is desired in the capacitor.
In a typical DRAM device available today, each memory cell includes one storage capacitor and one insulated gate field effect transistor (FET). The capacitor stores information in the form of electric charges which are recognizable by a digital information processing system as a "1" (e.g., charge present) or a "0" (e.g., no charge present). The transistor functions as a transfer gate, or switch, between the capacitor and a bit line.
The alpha particle component of normal background radiation can generate hole-electron pairs in the silicon substrate often employed for semiconductor devices, and the silicon substrate then functions as a capacitor plate. As a result, a charge stored within a capacitor of a memory cell may rapidly dissipate. This dissipation of charge from a memory cell is known as a "soft" error. To assure that a capacitor holds an electric charge, and to thereby reduce the "soft" error rate, the capacitance of the capacitor should preferably be as large as possible. The capacitance C of a capacitor may be expressed as: ##EQU1## where A=capacitor electrode area,
t=thickness of insulation layer between electrodes, and PA2 .epsilon.=dielectric constant of the insulation layer.
A counter-consideration to designing for maximum capacitance is a desire for highly integrating the memory device into which the capacitor is incorporated. To achieve a high degree of integration, it is desirable to reduce the planar area which the capacitor occupies on a semiconductor substrate. One approach may be to assure high capacitance by reducing the thickness t of the insulation layer. However, there are limits to the amount of reduction of such thickness; one must design sufficient thickness into the insulation layer to assure the layer truly acts as an adequate insulator to enable the structure to operate as a capacitor.
As previously mentioned, a trench capacitor is one solution to the dilemma of competing design requirements associated with increasing capacitance versus reducing "real estate" (i.e., surface area) occupied on a substrate. However, trench structures appropriate for capacitive functions require prolonged etch time. Further, in view of the durability of the etch mask, the depth of a trench (and, ergo, its capacitive capabilities) is subject to practical limitations.
In both general types of capacitive structures, trench capacitors and stacked capacitors, one approach to increasing capacitance without increasing "real estate" occupancy of the semiconductor substrate has been to create erose, or corrugated, surfaces in order to increase the area of the capacitor plates within a given lateral area.
Trench capacitors with a plurality of hollows to establish an erose, or corrugated structure in the side wall of the trench, and a method for manufacturing such a capacitive structure are known.
Stacked capacitors having erose, or corrugated, sides and methods for manufacturing such a capacitive structure are known.
However, a new method for manufacturing a stacked capacitive structure having erose, or corrugated sides is needed in the art to provide alternate cost considerations and alternate choices for process parameters than are presently available to designers and practitioners. For example, a method for manufacturing a corrugated stacked capacitive structure on a semiconductor substrate that first establishes a negative three dimensional image of the desired erose plate structure before establishing the positive structure in a sacrificial mandrel for later removal would be a useful alternative method for manufacturing an erose capacitive structure.